1. Field
Certain embodiments of the present disclosure generally relate to neural system engineering and, more particularly, to a method for power efficient implementation of neuron synapses with positive and/or negative weights.
2. Background
Neural system engineering has been attracting significant attention in recent years. Inspired by a biological brain with excellent flexibility and power efficiency, neural systems can be employed in many applications such as pattern recognition, machine learning and motor control. One of the biggest challenges of a practical neural system implementation is hardware density. Neurons and synapses are the two fundamental components of a neural system whose quantity can be as high as billions. As an example, a human brain has approximately 1011 neurons.
As a result, in order to implement practical neural systems, the neuron hardware is required to be extremely area efficient. In existing analog neuron implementations, area efficiency is limited by an integrating capacitor that mimics the neuron membrane capacitance. In order to design neurons operating with a time constant close to that of biological systems (e.g., approximately 1 ms), hundreds of fF capacitance is required even with minimal integrating current. Therefore, an area consumed by a single neuron can be quite large, especially with low-density on-chip capacitors (e.g., with densities of 2 to 11 fF/μm2).
Very Large Scale Integration (VLSI) implementation of brain computing devices also suffer from high power consumption due to a large number of neurons and even larger number of synaptic connections between the neurons. Technology scaling has allowed implementation of approximately one million neurons per chip. Each neuron can be connected to at least 1000 other neurons, which brings the number of synapses per chip to approximately one billion. In order to keep the power consumption low, each synapse should consume less than 100 nW. This is very challenging requirement and creates technology obstacle for VLSI implementation of brain computing devices.
A synaptic current that determines the strength of connection between neuron circuits is typically generated in the art by applying a fixed voltage across a variable resistor. However, this approach can lead to high power consumption, and only one type of the synaptic connection (excitatory or inhibitory) can be implemented.